Fan-out wafer-level packaging (FOWLP) is a key enabler in the industry shift from transistor scaling to system scaling and integration. The design fans out the chip interconnects through a redistribution layer instead of a substrate. Compared to flip-chip ball grid array (FCBGA) or wire bonds, it creates lower thermal resistance, a slimmer package, and potentially lower costs.
扇出晶圓級封裝 (FOWLP) 是行業(yè)從晶體管微縮向系統(tǒng)微縮和集成轉(zhuǎn)變的關(guān)鍵推動因素。該設(shè)計通過重新分布層而不是基板將芯片互連扇出。與倒裝芯片球柵陣列 (FCBGA) 或引線鍵合相比，它具有更低的熱阻、更纖薄的封裝以及潛在的更低成本。
Yet, if the hope is to reduce costs through eliminating substrates, the reality is that a lack of substrates can cause die shifts and warpage, undercutting the savings. Engineers are addressing die shift through improvements in lithography, pick-and-place, and molding operations — either thermocompression or laser bonding.
然而，如果希望通過消除基板來降低成本，那么現(xiàn)實情況是，缺少基板可能會導(dǎo)致芯片移位和翹曲，從而削弱成本節(jié)約。工程師們正在通過改進光刻、取放和成型操作（熱壓或激光鍵合）來解決芯片移位問題。
“It’s a great technology for one or two die,” said John Park, product management director for IC packaging at Cadence Design Systems. “But once you get to half a dozen chiplets or more, the limiting factor is die shift. Obviously, the more die you have, each one gets slightly shifted by a degree or two, and then you put six together and nothing connects anymore.”
Cadence Design Systems 的 IC 封裝產(chǎn)品管理總監(jiān) John Park 表示：“對于一兩個芯片而言，這是一項偉大的技術(shù)?！?“但是一旦你有了六個或更多的小芯片，限制因素就是芯片移位。顯然，你擁有的骰子越多，每個骰子都會稍微移動一兩度，然后你把六個骰子放在一起，就不再有任何聯(lián)系了。”
Nevertheless, issues such as long lead times for package substrates are accelerating FOWLP adoption. “Mobile and high performance computing/networking are a few areas where we see growing adoption beyond the low pin count, power management fan-out wafer level structure that has been traditionally the main FOLWP application,” said Mark Gerber, senior director, engineering and technical marketing at ASE.
然而，封裝基板交貨時間長等問題正在加速 FOWLP 的采用。 “除了傳統(tǒng)上主要的 FOLWP 應(yīng)用的低引腳數(shù)、電源管理扇出晶圓級結(jié)構(gòu)之外，移動和高性能計算/網(wǎng)絡(luò)是我們看到越來越多采用的幾個領(lǐng)域，”工程和高級總監(jiān) Mark Gerber 說道。 ASE 的技術(shù)營銷。
On balance, FOWLP is advancing as a solution. In Apple’s M1 Ultra chip, TSMC’s InFO fan-out process was chosen over a substrate-based process for its latest application processors (see figure 1). This is part of a broader trend. The market for fan-out packaging is expected to grow at a 15% compound annual growth rate, reaching $3.4B in 2026, according to Yole Développement. Yole analysts expect 93% of that capacity to be wafer-level packaging in 2025, and 7% to be processed at the panel level.
總而言之，F(xiàn)OWLP 作為一種解決方案正在不斷發(fā)展。在 Apple 的 M1 Ultra 芯片中，其最新應(yīng)用處理器選擇了臺積電的 InFO 扇出工藝，而不是基于基板的工藝（見圖 1）。這是更廣泛趨勢的一部分。據(jù) Yole Développement 稱，扇出型封裝市場預(yù)計將以 15% 的復(fù)合年增長率增長，到 2026 年將達到 $3.4B。 Yole 分析師預(yù)計，到 2025 年，其中 93% 的產(chǎn)能將用于晶圓級封裝，7% 將用于面板級加工。
Fig. 1: State-of-the-art RDL connecting to via in TSMC’s InFO and Deca’s M-Series. Source: Deca
圖 1：最先進的 RDL 連接到 TSMC 的 InFO 和 Deca 的 M 系列中的過孔。來源：德卡
Other products in volume production today include RF devices, power management ICs (PMICs), baseband processors, and high-end server chips. 5G should further boost the adoption of fan-out packaging because the shorter interconnects and lower inductance lead to superior RF and millimeter-wave performance.
目前量產(chǎn)的其他產(chǎn)品包括射頻器件、電源管理 IC (PMIC)、基帶處理器和高端服務(wù)器芯片。 5G 應(yīng)進一步推動扇出封裝的采用，因為更短的互連和更低的電感可帶來卓越的射頻和毫米波性能。
“There’s been a lot of discussion and modeling of FOWLP for millimeter wave antenna and millimeter wave packaging,” said Dr. Monita Pau, strategic marketing director for advanced packaging at Onto Innovation. “That makes the dielectric material a very important element. You must have very good mechanical properties and very low loss dielectric properties, because you’re integrating a millimeter wave antenna together with the fan-out packages. Additionally, low copper RDL roughness and lithographic techniques that adapt to topography are needed to achieve good CD uniformity of the redistribution layer, which is critical to achieving high gain and low loss transfer.”
“針對毫米波天線和毫米波封裝的 FOWLP 有很多討論和建模，”O(jiān)nto Innovation 先進封裝戰(zhàn)略營銷總監(jiān) Monita Pau 博士說。 “這使得介電材料成為一個非常重要的元素。您必須具有非常好的機械性能和非常低的介電性能損耗，因為您要將毫米波天線與扇出封裝集成在一起。此外，需要低銅 RDL 粗糙度和適應(yīng)形貌的光刻技術(shù)來實現(xiàn)重新分布層的良好 CD 均勻性，這對于實現(xiàn)高增益和低損耗傳輸至關(guān)重要?！?/font>
Fan out’s roots 扇出根部
Fan-outs have a long history. This packaging approach was first introduced in 2007, when Infineon devised its embedded wafer-level BGA (eWLB). But the first wave of adoption followed TSMC’s use of InFO in the iPhone 7 in 2016. “If we look at wafer level packaging in general, the smartphone has really driven that space more than any other single product,” said Jan Vardaman, president of TechSearch International.
扇出有著悠久的歷史。這種封裝方法于 2007 年首次推出，當(dāng)時英飛凌設(shè)計了嵌入式晶圓級 BGA (eWLB)。但第一波采用浪潮是在 2016 年臺積電在 iPhone 7 中使用 InFO 之后?！叭绻覀兛傮w上看一下晶圓級封裝，智能手機確實比任何其他單一產(chǎn)品都更能推動這一領(lǐng)域的發(fā)展，”公司總裁 Jan Vardaman 說道。技術(shù)搜索國際。
While cell phones have been the canonical use case ever since the iPhone 7, the FOWLP design also can scale up for devices like supercomputers. Newer applications include network switching products, PMICs for phones and smart watches, and AI chips.
雖然自 iPhone 7 以來手機一直是典型的用例，但 FOWLP 設(shè)計也可以擴展到超級計算機等設(shè)備。較新的應(yīng)用包括網(wǎng)絡(luò)交換產(chǎn)品、手機和智能手表的 PMIC 以及人工智能芯片。
For assembly in high-end applications, OSATs and foundries are coupling fan-out packaging together with a substrate. “Before people used to say you didn’t need to use a substrate, you can just directly attach it to the board, but now because of the high-density requirements, they need a substrate before it can be attached to the PCB board,” said Pau.
為了在高端應(yīng)用中進行組裝，OSAT 和代工廠將扇出封裝與基板耦合在一起。 “以前人們說不需要使用基板，直接將其貼到板上即可，但現(xiàn)在由于高密度的要求，他們需要基板才能貼到PCB板上， ”保羅說。
Today’s FOWLP designs also enable a more flexible design. Gerber said, “Our Fan Out Chip on Substrate Bridge (FOCoS-B) pillar can integrate one or more die in between redistribution layers, integrating deep trench capacitors, voltage regulators, etc., in very close proximity to the active silicon circuitry. This minimizes system level loss for higher performance.”
如今的 FOWLP 設(shè)計還可以實現(xiàn)更靈活的設(shè)計。 Gerber 表示：“我們的扇出基板橋芯片 (FOCoS-B) 支柱可以在重新分布層之間集成一個或多個芯片，在非?？拷性垂桦娐返奈恢眉缮顪喜垭娙萜?、穩(wěn)壓器等。這可以最大限度地減少系統(tǒng)級損失，從而實現(xiàn)更高的性能?！?/font>
Process 過程
There are two categories of fan-out process flows, die first (also called mold first) and RDL first (see figure 2). Dies also can be placed face up or face down on the carrier wafer or panel.
扇出工藝流程有兩類：先裸片（也稱為先模）和先 RDL（見圖 2）。芯片也可以面朝上或面朝下放置在載體晶圓或面板上。
Fig. 2: Process flows for chip first (mold first) configuration and RDL first. Source: Fraunhofer IZM
圖 2：先芯片（先模具）配置和先 RDL 的工藝流程。資料來源：弗勞恩霍夫 IZM
In die first, thermal release tape is applied to a carrier wafer, then the known good die (KGD) are picked and placed on the carrier. Next, overmolding is followed by carrier release, RDL formation, solder bumping, then singulation. In RDL first, the release layer again is deposited first, then the RDL, KGD positioning is followed by overmold, carrier release, solder ball deposition, and singulation.
首先在芯片中，將熱剝離膠帶粘貼到載體晶圓上，然后拾取已知良好的芯片 (KGD) 并將其放置在載體上。接下來，包覆成型之后是載體釋放、RDL 形成、焊料凸點，然后是分割。首先在 RDL 中，再次沉積釋放層，然后進行 RDL、KGD 定位，然后進行包覆成型、載體釋放、焊球沉積和分割。
While fan-out starts with classic assembly techniques, it also requires non-traditional processes. “It adds things that you don’t normally see, like compression molding onto the reconstituted wafer to fill in areas, and then grinding the plastic material mold compound as opposed to backgrinding a wafer,” said Chip Greely, vice president of engineering at Promex Industries, the parent company of QP Technologies. “Then you deposit a copper redistribution layer on top of that, which gets you three factors away from what some assembly houses are comfortable with. Typically, when you’re backgrinding silicon or any of those crystal materials, they tend to granulate and wash out very easily. Mold compound tends to gum and ball up, so your grinding wheel gets loaded up with plastic, requiring a secret sauce to remove it.” Nevertheless, he says, with enough devices, the economies of scale work.
雖然扇出始于經(jīng)典的組裝技術(shù)，但它也需要非傳統(tǒng)的工藝。 Promex 工程副總裁 Chip Greely 表示：“它增加了您通?？床坏降臇|西，例如在重組晶圓上壓縮成型以填充區(qū)域，然后研磨塑料材料模塑料，而不是背面研磨晶圓?！?Industries，QP Technologies 的母公司。 “然后你在上面沉積一個銅重新分布層，這會讓你遠離一些裝配廠所滿意的三個因素。通常，當(dāng)您對硅或任何這些晶體材料進行背面研磨時，它們很容易顆粒化并被洗掉。模塑料往往會粘在一起并成球，因此您的砂輪上會沾滿塑料，需要一種秘密醬汁才能將其去除?！北M管如此，他表示，只要有足夠的設(shè)備，規(guī)模經(jīng)濟就會發(fā)揮作用。
The reason fan-out has gained such popularity relative to fan-in WLP is because it accommodates more I/O connections. The state-of-the-art fan out package today features RDLs of up to five-layers (see figure 3), with down to 2μm lines and spaces (the width and pitch of metal traces). Scaling to the micron interconnect range means the RDL process is beginning to look more like on-chip dual damascene integration.
扇出相對于扇入 WLP 如此受歡迎的原因是它可容納更多 I/O 連接。目前最先進的扇出封裝具有高達五層的 RDL（見圖 3），線路和間距（金屬跡線的寬度和間距）低至 2μm。擴展到微米互連范圍意味著 RDL 工藝開始看起來更像片上雙鑲嵌集成。
Fig. 3: Redistribution layers consist of copper traces in polyimide dielectric. Source: Lam Research
圖 3：重新分布層由聚酰亞胺電介質(zhì)中的銅跡線組成。資料來源：泛林研究
For example, Amkor recently revealed an embedded trace RDL (ETR) for its S-SWIFT fan-out technology that enables scaling to less than 2/1 line/space and vias.[1] The new process integrates an ASIC with two high-bandwidth memory (HBM) chips. Innovations include a through-mold copper pillar, high-density RDL, uniform dielectric coating, optimized copper plating, CMP, and wet etch to enable a simpler, more extendible process than its process of record (POR).
例如，Amkor 最近為其 S-SWIFT 扇出技術(shù)推出了嵌入式走線 RDL (ETR)，可將線/間距和過孔縮放至小于 2/1。 [1]新工藝將 ASIC 與兩個高帶寬內(nèi)存 (HBM) 芯片集成在一起。創(chuàng)新包括通模銅柱、高密度 RDL、均勻介電涂層、優(yōu)化鍍銅、CMP 和濕法蝕刻，以實現(xiàn)比其記錄工藝 (POR) 更簡單、更可擴展的工藝。
Amkor Vice President SangHyun Jin and his team improved on the POR, a semi-additive process (see figure 4a). Process changes were explored to overcome potential for high AR trace collapse, photoresist residue in vias and sidewall etch issues.
Amkor 副總裁 SangHyun Jin 及其團隊改進了 POR，這是一種半加成工藝（見圖 4a）。我們探索了工藝改變，以克服高 AR 跡線塌陷、通孔中光刻膠殘留和側(cè)壁蝕刻問題的可能性。
The Amkor team first developed a dual-damascene process (figure 4b) that embeds the copper trace in a polymer layer. This change improves adhesion of the RDL to substrate and by depositing barrier layer on three sides of the trench, reliability is enhanced. The team noted that the vias and RDL were separately formed by a two-pass lithography process using spin coat of an organic dielectric. After curing, the seed layer and copper were plated, followed by CMP and wet etch.
Amkor 團隊首先開發(fā)了一種雙鑲嵌工藝（圖 4b），將銅跡線嵌入聚合物層中。這一變化提高了 RDL 與基板的粘附力，并且通過在溝槽的三個側(cè)面沉積阻擋層，提高了可靠性。該團隊指出，通孔和 RDL 是通過使用有機電介質(zhì)旋涂的兩次光刻工藝分別形成的。固化后，電鍍種子層和銅，然后進行 CMP 和濕法蝕刻。
The final process (figure 4c) combines the via and RDL patterning into one mask, reducing process steps by 40%. This change also eliminated misalignment between the via and capture pad. The three-step CMP process was changed to single CMP, followed by wet etch. CMP ensured flatter profiles for each RDL and 2μm line with 1μm spaces were fabricated on a four-layer RDL, with extendibility to six layers. Following assembly, the engineers performed reliability testing on the heterogenous devices.
最終工藝（圖 4c）將通孔和 RDL 圖案化合并到一個掩模中，從而減少了 40% 的工藝步驟。這一變化還消除了通孔和定位焊盤之間的錯位。三步 CMP 工藝改為單步 CMP，然后進行濕法蝕刻。 CMP 確保每個 RDL 具有更平坦的輪廓，并在四層 RDL 上制造具有 1μm 間距的 2μm 線，并可擴展到六層。組裝后，工程師對異構(gòu)設(shè)備進行了可靠性測試。
Fig. 4: An RDL semi-additive process (a), was modified to dual damascene (b) and then simplified damascene (c) process that is extendible to 2/1μm line/space traces. Source: Amkor
圖 4：RDL 半加成工藝 (a) 修改為雙鑲嵌 (b)，然后簡化鑲嵌 (c) 工藝，可擴展到 2/1μm 線/空間跡線。來源：Amkor
Also at ECTC, Lihong Cao, director of engineering at ASE, and her team showed how fan out to RDLs can be used to reduce the complexity and cost of ASICs on multilayer organic interposer (ABF) substrates. [2] ASE was able to convert a 14-layer substrate to 8 layers with 2 RDLs. A second test device showed a 10-layer substrate was reduced to 4 layers using 1 RDL. Such changes will reduce the cost and yield loss associated with increasingly complex substrates.
同樣在 ECTC，ASE 工程總監(jiān) Lihong Cao 和她的團隊展示了如何使用扇出至 RDL 來降低多層有機中介層 (ABF) 基板上 ASIC 的復(fù)雜性和成本。 [2] ASE 能夠?qū)?14 層基板轉(zhuǎn)換為具有 2 個 RDL 的 8 層基板。第二個測試設(shè)備顯示，使用 1 個 RDL 將 10 層基板減少為 4 層。這些變化將降低與日益復(fù)雜的基板相關(guān)的成本和產(chǎn)量損失。
Die shift 模具移位
Die shift can occur at any point after dies are picked and placed on the carrier wafer, but the biggest risk is during molding compound processing, which can impact yield.
在拾取芯片并將其放置到載體晶圓上后的任何時刻都可能發(fā)生芯片移位，但最大的風(fēng)險是在模塑料加工過程中，這可能會影響良率。
Die shift can be reduced by using laser assisted bonding or thermocompression bonding in place of conventional mass flow. Another method is Adaptive Patterning, created by Deca and built into Cadence’s EDA tools. It will soon be available for Synopsys and Siemens EDA tools. In adaptive patterning (see figure 5), the process engineer measures the die and interconnect positions precisely on the lithography tool, then the deposited RDL pattern is adapted to those positions.
通過使用激光輔助鍵合或熱壓鍵合代替?zhèn)鹘y(tǒng)的質(zhì)量流可以減少芯片移位。另一種方法是自適應(yīng)模式，由 Deca 創(chuàng)建并內(nèi)置于 Cadence 的 EDA 工具中。它很快將可用于 Synopsys 和西門子 EDA 工具。在自適應(yīng)圖案化中（見圖 5），工藝工程師在光刻工具上精確測量芯片和互連位置，然后沉積的 RDL 圖案適應(yīng)這些位置。
Fig. 5: Adaptive Patterning aligns the vias and RDL contacts with the actual location of the die. Source: Deca
圖 5：自適應(yīng)圖案化將過孔和 RDL 觸點與芯片的實際位置對齊。來源：德卡
“In the design process you determine which AP techniques will most optimally help you to scale to higher density or adjust the manufacturing process capability to achieve 100% yield, or very close to it,” said Tim Olson, CEO of Deca Technologies. “So there are decisions you make in the design process regarding which manufacturing factory is going to be used. Once you release the design to manufacturing, the patterning engine at our licensees in Taiwan, the Philippines, and Korea have servers whereby on each wafer, or each panel, we do high-speed optical scans to locate the I/Os. The engine takes the design instructions on one of those EDA systems, and then it executes per RDL layer, doing either alignment or optimization. In some cases, it’s redrawn to accommodate shift.” Finally, the GDSII file is converted into a digital bitmap and used by a compatible maskless lithography tool to print the aligned connections.
Deca Technologies 首席執(zhí)行官 Tim Olson 表示：“在設(shè)計過程中，您需要確定哪種 AP 技術(shù)能夠最有效地幫助您擴展到更高的密度或調(diào)整制造工藝能力，以實現(xiàn) 100% 的良率或非常接近 100% 的良率。” “因此，您在設(shè)計過程中需要做出關(guān)于將使用哪個制造工廠的決定。一旦您將設(shè)計發(fā)布到制造階段，我們在臺灣、菲律賓和韓國的授權(quán)商的圖案化引擎就會配備服務(wù)器，我們可以在每個晶圓或每個面板上進行高速光學(xué)掃描來定位 I/O。該引擎在其中一個 EDA 系統(tǒng)上獲取設(shè)計指令，然后在每個 RDL 層上執(zhí)行，進行對齊或優(yōu)化。在某些情況下，它會被重新繪制以適應(yīng)轉(zhuǎn)變?！弊詈?，GDSII 文件被轉(zhuǎn)換為數(shù)字位圖，并由兼容的無掩模光刻工具用來打印對齊的連接。
“We have a new approach that eliminates capture pads,” Olson noted. “Capture pads were invented to take up overlay tolerances. With adaptive patterning, we can achieve breakthrough density without the use of capture pads.” He added that the specification on pick-and-place only needs to be 15μm, whereas much higher accuracy is needed without adaptive patterning, which lowers tool throughput significantly.
“我們有一種消除捕獲墊的新方法，”奧爾森指出。 “捕獲墊的發(fā)明是為了吸收重疊公差。通過自適應(yīng)圖案化，我們可以在不使用捕獲墊的情況下實現(xiàn)突破性的密度?！彼a充說，取放規(guī)格只需 15μm，而無需自適應(yīng)圖案化則需要更高的精度，這會顯著降低工具吞吐量。
Die shift is also addressed by refining the choice of bonding material, as Brewer Science explains: “In order for bonding materials to maintain minimal vertical deformation during die placement and minimal die shift during over-molding, they have to have high melt viscosity and high thermal stability. This is particularly important due to the mismatch between the coefficients of thermal expansion (CTEs) of the carrier and substrate material. Bonding materials have to also be customized in a way that minimizes stress effects in stacked wafers, where warpage might occur, resulting in issues of alignment and handling. They should have sufficient adhesion to the substrate material to be able to tolerate such stresses.”
芯片移位也可以通過改進粘合材料的選擇來解決，正如 Brewer Science 所解釋的那樣：“為了使粘合材料在芯片放置過程中保持最小的垂直變形以及在包覆成型過程中保持最小的芯片移位，它們必須具有高熔體粘度和高熔體粘度?！睙岱€(wěn)定性。由于載體和基板材料的熱膨脹系數(shù) (CTE) 不匹配，這一點尤為重要。接合材料還必須以最小化堆疊晶圓中的應(yīng)力影響的方式進行定制，堆疊晶圓中可能會發(fā)生翹曲，從而導(dǎo)致對準(zhǔn)和處理問題。它們應(yīng)該對基材有足夠的粘附力，以便能夠承受這樣的應(yīng)力?！?/font>
Stress and warpage
應(yīng)力和翹曲The mismatch of CTE between silicon, polyimide (in RDL), and epoxy molding compound creates warpage problems. Warpage leads to yield loss.
硅、聚酰亞胺（RDL 中）和環(huán)氧模塑料之間的 CTE 不匹配會產(chǎn)生翹曲問題。翹曲會導(dǎo)致良率損失。
“Warpage is definitely a problem. That’s why a lot of the individuals are moving to the compression molding and the bottom gated, compression molding versus the top system,” said Greely.
“翹曲絕對是一個問題。這就是為什么很多人轉(zhuǎn)向壓縮成型和底部澆口壓縮成型而不是頂部系統(tǒng)，”Greely 說。
Another way to reduce stress and warping is by selecting better dielectric material with lower cure temperatures.
減少應(yīng)力和翹曲的另一種方法是選擇具有較低固化溫度的更好介電材料。
Going to panels? 去面板？
Fan-out panel-level packaging (FOPLP) is an extension of wafer-level fan out that capitalizes on the larger substrate size of 510 x 515mm or 600 x 600mm, the SEMI standard sizes. Samsung got early buzz with its 2018 FOPLP for the Galaxy watch. Nepes launched the first fan-out panel-level packaging operation in Phillippines last year using 600 x 600um panels. Samsung, Powertech, Unimicron, and ASE either already have, or soon will have, FOPLP in volume production.
扇出面板級封裝 (FOPLP) 是晶圓級扇出封裝的延伸，它利用了 SEMI 標(biāo)準(zhǔn)尺寸 510 x 515 毫米或 600 x 600 毫米的較大基板尺寸。三星憑借其 2018 年 Galaxy 手表 FOPLP 引起了廣泛關(guān)注。 Nepes 去年在菲律賓推出了首個使用 600 x 600um 面板的扇出面板級封裝業(yè)務(wù)。三星、Powertech、Unimicron 和 ASE 已經(jīng)或即將實現(xiàn) FOPLP 的量產(chǎn)。
Though these companies appear to be moving forward, FOPLP is largely on hold until volumes dictate the need for a massive conversion from wafer carriers to panel-level processing. It’s unclear when that will change. “If they say five years is a window of opportunity, I would at least triple it,” said Greely. “Panelization is such a great idea, but there are challenges when you get into the details. It’s like telling people that we’re going to have a standardized chiplet.”
盡管這些公司似乎正在向前發(fā)展，但 FOPLP 基本上處于擱置狀態(tài)，直到產(chǎn)量表明需要從晶圓載體大規(guī)模轉(zhuǎn)換為面板級處理。目前尚不清楚這種情況何時會改變。 “如果他們說五年是一個機會之窗，我至少會把它增加三倍，”格里利說。 “面板化是一個好主意，但當(dāng)你深入細節(jié)時就會遇到挑戰(zhàn)。這就像告訴人們我們將擁有標(biāo)準(zhǔn)化的小芯片?！?/font>
Design 設(shè)計
While panels may still be in the future, the basic FOWLP layout has become so accepted that automated design tools already are well-established. Cadence has certified design flows with well-known foundries, according to Park, and will announce further developments at the upcoming LIP.
雖然面板可能仍處于未來階段，但基本的 FOWLP 布局已被廣泛接受，自動化設(shè)計工具已經(jīng)成熟。 Park 表示，Cadence 已與知名代工廠認證了設(shè)計流程，并將在即將舉行的 LIP 上宣布進一步的開發(fā)成果。
However, packages are a different world from laminates, cautions Park. For example, packages come with unique types of design rules, such as “zigzag insertion,” which is the need for a break in a lateral line to improve yield.
然而，Park 警告說，封裝與層壓板是不同的世界。例如，封裝具有獨特類型的設(shè)計規(guī)則，例如“之字形插入”，即需要在側(cè)線中中斷以提高產(chǎn)量。
“Traditional packaging tools output Gerber file formats (.grb), which are manufacturing formats for laminate substrates, not wafers,” said Park. “When you build a laminate, there is no formal sign off process, like DRC and LBF, as there is when building a wafer.”
“傳統(tǒng)封裝工具輸出 Gerber 文件格式 (.grb)，這是層壓基板而不是晶圓的制造格式，”Park 說。 “當(dāng)你構(gòu)建層壓板時，沒有像構(gòu)建晶圓時那樣的 DRC 和 LBF 等正式簽核流程?！?/font>
To address this problem, Cadence has created an extension that links IC verification tools with package physical design tools. “If someone is new to the IC world, they can just pick the rules they want to check against in a GUI, and the tool will do the LBS and DRC. And then, any results from that run will be presented back to the user inside the layout tool,” said Park.
為了解決這個問題，Cadence 創(chuàng)建了一個擴展，將 IC 驗證工具與封裝物理設(shè)計工具鏈接起來。 “如果有人是 IC 世界的新手，他們只需在 GUI 中選擇想要檢查的規(guī)則，該工具就會執(zhí)行 LBS 和 DRC。然后，該運行的任何結(jié)果都將在布局工具內(nèi)呈現(xiàn)給用戶，”Park 說。
There are additional issues that can challenge engineers, regardless of their prior experience. “The requirements for ultra-high density RDLs, such as are found in TSMC’s inFO, are much more stringent than anything package designers have had to deal with in the past,” he said. Design tools are now taking into account metal balancing, with such issues as voiding pads and vias and degassing copper fill areas.
無論工程師以前的經(jīng)驗如何，還有其他問題可能會給他們帶來挑戰(zhàn)。 “對超高密度 RDL 的要求（例如臺積電的 inFO 中的要求）比封裝設(shè)計人員過去必須處理的任何要求都要嚴(yán)格得多，”他說。設(shè)計工具現(xiàn)在正在考慮金屬平衡，以及諸如焊盤和通孔空洞以及銅填充區(qū)域脫氣等問題。
Finally, there’s conductivity verification, which can be extremely complex when multiple chiplets are involved. “It may come at the last stage of production,” said Park, “But you have to think about it early on, because that net list that drives the LVS has to be built in the early stages of the design.”
最后，還有電導(dǎo)率驗證，當(dāng)涉及多個小芯片時，這可能會非常復(fù)雜。 “它可能會在生產(chǎn)的最后階段出現(xiàn)，”Park 說，“但你必須盡早考慮它，因為驅(qū)動 LVS 的網(wǎng)絡(luò)列表必須在設(shè)計的早期階段構(gòu)建。”
Conclusion 結(jié)論
The industry is finding multiple ways to use fan out packaging to streamline packages and simplify processes. “We had a customer replace a 12-layer substrate with a 5-layer RDL, and at the same time the body size shrank by 20%,” said Deca’s Olson. “Fan out is currently more expensive than the substrate solutions, but if you’re able to reduce the layer count, it’s very cost-competitive.”
業(yè)界正在尋找多種方法來使用扇出封裝來簡化封裝和簡化流程。 “我們讓客戶用 5 層 RDL 替換了 12 層基板，同時機身尺寸縮小了 20%，”Deca 的 Olson 說道。 “扇出目前比基板解決方案更昂貴，但如果能夠減少層數(shù)，則非常具有成本競爭力?！?/font>
Vardaman sees both chip first and chip last schemes being required going forward. “Everything is about picking the right package and the right structure for what you’re trying to do.”
Vardaman 認為未來需要芯片優(yōu)先和芯片最后兩種方案。 “一切都是為了為你想要做的事情選擇正確的包和正確的結(jié)構(gòu)。”
References 參考
[1] S. Jin, et. al., “Substrate Silicon Wafer Integrated Fan-out Technology (S-SWIFT) Packaging with Fine Pitch Embedded Trace RDL,” IEEE 71st Electronic Components and Technology Conference (ECTC), 2022, doi: 10.1109/ECTC51906.2022.00218
[1]金圣，等。 al.，“具有細間距嵌入式走線 RDL 的基板硅晶圓集成扇出技術(shù) (S-SWIFT) 封裝”，IEEE 71 st 電子元件和技術(shù)會議 (ECTC)，2022 年，doi：10.1109/ ECTC51906.2022.00218
[2] L. Cao, et., al., “Advanced Fanout Packaging Technology for Hybrid Substrate Integration,” IEEE 71st Electronic Components and Technology Conference (ECTC), 2022, doi: 10.1109/ECTC51906.2022.00219
[2] L. Cao 等人，“用于混合基板集成的高級扇出封裝技術(shù)”，IEEE 71 st 電子元件和技術(shù)會議 (ECTC)，2022 年，doi：10.1109/ECTC51906。 2022.00219
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